arm-8: boot.s에서 사용한 smdk2440을 위한 코드

memcfg.inc

;************************************************
; NAME    : MEMCFG.A
; DESC          : Memory bank configuration file
; Revision: 02.28.2002 ver 0.0
; Revision: 03.11.2003 ver 0.0        Attatched for 2440
;************************************************

;Memory Area
;GCS6 32bit(64MB) SDRAM(0x3000_0000-0x33ff_ffff)


;BWSCON
DW8                        EQU        (0x0)
DW16                EQU        (0x1)
DW32                EQU        (0x2)
WAIT                EQU        (0x1<<2)
UBLB                EQU        (0x1<<3)

        ASSERT :DEF:BUSWIDTH
    [ BUSWIDTH=16
B1_BWSCON        EQU (DW16)
B2_BWSCON        EQU (DW16)
B3_BWSCON        EQU (DW16)
B4_BWSCON        EQU (DW16)
B5_BWSCON        EQU (DW16)
B6_BWSCON        EQU (DW16)
B7_BWSCON        EQU (DW16)
    | ;BUSWIDTH=32                ; 2440 EV board.
B1_BWSCON        EQU (DW16)        ; AMD flash(AM29LV800B), 16-bit,  for nCS1
B2_BWSCON        EQU (DW16)        ; PCMCIA(PD6710), 16-bit
B3_BWSCON        EQU (DW16)        ; Ethernet(CS8900), 16-bit
B4_BWSCON        EQU (DW32)        ; Intel Strata(28F128), 32-bit, for nCS4
B5_BWSCON        EQU (DW16)        ; A400/A410 Ext, 16-bit
B6_BWSCON        EQU (DW32)        ; SDRAM(K4S561632C) 32MBx2, 32-bit
B7_BWSCON        EQU (DW32)        ; N.C.
    ]

;BANK0CON

B0_Tacs                EQU        0x0        ;0clk
B0_Tcos                EQU        0x0        ;0clk
B0_Tacc                EQU        0x7        ;14clk
B0_Tcoh                EQU        0x0        ;0clk
B0_Tah                EQU        0x0        ;0clk
B0_Tacp                EQU        0x0
B0_PMC                EQU        0x0        ;normal

;BANK1CON
B1_Tacs                EQU        0x0        ;0clk
B1_Tcos                EQU        0x0        ;0clk
B1_Tacc                EQU        0x7        ;14clk
B1_Tcoh                EQU        0x0        ;0clk
B1_Tah                EQU        0x0        ;0clk
B1_Tacp                EQU        0x0
B1_PMC                EQU        0x0        ;normal

;Bank 2 parameter
B2_Tacs                EQU        0x0        ;0clk
B2_Tcos                EQU        0x0        ;0clk
B2_Tacc                EQU        0x7        ;14clk
B2_Tcoh                EQU        0x0        ;0clk
B2_Tah                EQU        0x0        ;0clk
B2_Tacp                EQU        0x0
B2_PMC                EQU        0x0        ;normal

;Bank 3 parameter
B3_Tacs                EQU        0x0        ;0clk
B3_Tcos                EQU        0x0        ;0clk
B3_Tacc                EQU        0x7        ;14clk
B3_Tcoh                EQU        0x0        ;0clk
B3_Tah                EQU        0x0        ;0clk
B3_Tacp                EQU        0x0
B3_PMC                EQU        0x0        ;normal

;Bank 4 parameter
B4_Tacs                EQU        0x0        ;0clk
B4_Tcos                EQU        0x0        ;0clk
B4_Tacc                EQU        0x7        ;14clk
B4_Tcoh                EQU        0x0        ;0clk
B4_Tah                EQU        0x0        ;0clk
B4_Tacp                EQU        0x0
B4_PMC                EQU        0x0        ;normal

;Bank 5 parameter
B5_Tacs                EQU        0x0        ;0clk
B5_Tcos                EQU        0x0        ;0clk
B5_Tacc                EQU        0x7        ;14clk
B5_Tcoh                EQU        0x0        ;0clk
B5_Tah                EQU        0x0        ;0clk
B5_Tacp                EQU        0x0
B5_PMC                EQU        0x0        ;normal

        [ {TRUE}        ; When 100MHz HCLK is used.
;Bank 6 parameter
B6_MT                EQU        0x3        ;SDRAM
B6_Trcd                EQU        0x1        ;3clk
B6_SCAN                EQU        0x1        ;9bit

;Bank 7 parameter
B7_MT                EQU        0x3        ;SDRAM
B7_Trcd                EQU        0x1        ;3clk
B7_SCAN                EQU        0x1        ;9bit

;REFRESH parameter
REFEN                EQU        0x1        ;Refresh enable
TREFMD                EQU        0x0        ;CBR(CAS before RAS)/Auto refresh
Trp                        EQU        0x1        ;3clk
Tsrc                EQU        0x1        ;5clk        Trc= Trp(3)+Tsrc(5) = 8clock
Tchr                EQU        0x2        ;3clk
REFCNT                EQU        1269        ;HCLK=105Mhz, (2048+1-7.8*100)

        |
;Bank 6 parameter
B6_MT                EQU        0x3        ;SDRAM
B6_Trcd                EQU        0x2        ;4clk
B6_SCAN                EQU        0x1        ;9bit

;Bank 7 parameter
B7_MT                EQU        0x3        ;SDRAM
B7_Trcd                EQU        0x2        ;4clk
B7_SCAN                EQU        0x1        ;9bit

;REFRESH parameter
REFEN                EQU        0x1        ;Refresh enable
TREFMD                EQU        0x0        ;CBR(CAS before RAS)/Auto refresh
Trp                        EQU        0x2        ;4clk
Tsrc                EQU        0x2        ;6clk        Trc= Trp(4)+Tsrc(6) = 10clock

Tchr                EQU        0x2        ;3clk
REFCNT                EQU        1012        ;HCLK=135Mhz, (2048+1-7.8*133 = 1012)
        ]
        
        END
-----------------------------------------------------------------------
Option.inc

;===========================================
; NAME: OPTION.A
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
; 03.11.2003: ver 0.0        attached for 2440.
; jan E, 2004: ver0.03  modified for 2440A01.
;===========================================

;Start address of each stacks,
_STACK_BASEADDRESS        EQU 0x33ff8000
_MMUTT_STARTADDRESS        EQU 0x33ff8000
_ISR_STARTADDRESS        EQU 0x33ffff00

                GBLL         PLL_ON_START
PLL_ON_START        SETL         {TRUE}


                GBLL        ENDIAN_CHANGE
ENDIAN_CHANGE        SETL        {FALSE}

                GBLA        ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH        SETA        16


;BUSWIDTH = 16,32
                GBLA    BUSWIDTH        ;max. bus width for the GPIO

configuration
BUSWIDTH        SETA    32

                GBLA        UCLK
UCLK        SETA        48000000

                GBLA        XTAL_SEL
                GBLA        FCLK
                GBLA        CPU_SEL

;(1) Select CPU                
;CPU_SEL        SETA        32440000        ; 32440000:2440X.
CPU_SEL        SETA        32440001        ; 32440001:2440A

;(2) Select XTaL
;XTAL_SEL        SETA        12000000
XTAL_SEL        SETA        16934400

;(3) Select FCLK
;FCLK                SETA        304000000
FCLK                SETA        296352000

;(4) Select Clock Division (Fclk:Hclk:Pclk)
CLKDIV_VAL        EQU        7        ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4,

4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
        


[ XTAL_SEL = 12000000

        [ FCLK = 271500000
M_MDIV                EQU        173                ;Fin=12.0MHz Fout=271.5MHz
M_PDIV                EQU        2
                [ CPU_SEL = 32440001
M_SDIV                EQU        2                ; 2440A
                   |
M_SDIV                EQU        1                ; 2440X
                   ]
        ]
        
        [ FCLK = 304000000
M_MDIV                EQU        68                ;Fin=12.0MHz Fout=304.8MHz
M_PDIV                EQU        1
                [ CPU_SEL = 32440001
M_SDIV                EQU        1                ; 2440A
                |
M_SDIV                EQU        0                ; 2440X
                ]
        ]


        [ UCLK = 48000000
U_MDIV                EQU        56                ;Fin=12.0MHz Fout=48MHz
U_PDIV                EQU        2
                [ CPU_SEL = 32440001
U_SDIV                EQU        2                ; 2440A
                   |
U_SDIV                EQU        1                ; 2440X
                   ]
        ]
        [ UCLK = 96000000
U_MDIV                EQU        56                ;Fin=12.0MHz Fout=96MHz
U_PDIV                EQU        2
                [ CPU_SEL = 32440001
U_SDIV                EQU        1                ; 2440A
                   |
U_SDIV                EQU        0                ; 2440X
                   ]

        ]

  |        ; else if XTAL_SEL = 16.9344Mhz

        [ FCLK = 266716800
M_MDIV                EQU        118        ;Fin=16.9344MHz
M_PDIV                EQU        2
                [ CPU_SEL = 32440001
M_SDIV                EQU        2                ; 2440A
                |
M_SDIV                EQU        1                ; 2440X
                ]
        ]
        
        [ FCLK = 296352000
M_MDIV                EQU        97        ;Fin=16.9344MHz
M_PDIV                EQU        1
                [ CPU_SEL = 32440001
M_SDIV                EQU        2                ; 2440A
                |
M_SDIV                EQU        1                ; 2440X
                ]
        ]
        [ FCLK = 541900800
M_MDIV                EQU        120        ;Fin=16.9344MHz
M_PDIV                EQU        2
                [ CPU_SEL = 32440001
M_SDIV                EQU        1                ; 2440A
                |
M_SDIV                EQU        0                ; 2440X
                ]
        ]
        
        [ UCLK = 48000000
U_MDIV                EQU        60        ;Fin=16.9344MHz Fout=48MHz
U_PDIV                EQU        4
                [ CPU_SEL = 32440001
U_SDIV                EQU        2                ; 2440A
                   |
U_SDIV                EQU        1                ; 2440X
                   ]
           ]
        [ UCLK = 96000000
U_MDIV                EQU        60        ;Fin=16.9344MHz Fout=96MHz
U_PDIV                EQU        4
                [ CPU_SEL = 32440001
U_SDIV                EQU        1                ; 2440A
                   |
U_SDIV                EQU        0                ; 2440X
                   ]
        ]
        
   ]        ; end of if XTAL_SEL = 12000000.
  



        END
-----------------------------------------------------------------------
2440addr.inc

;====================================================================
; File Name : 2440addr.a
; Function  : S3C2440 Define Address Register (Assembly)
; Date      : March 27, 2002
; Revision        : Programming start (February 18,2002) -> SOP
; Revision        : 03.11.2003 ver 0.0        Attatched for 2440
;====================================================================

        GBLL   BIG_ENDIAN__
BIG_ENDIAN__   SETL   {FALSE}

;=================
; Memory control
;=================
BWSCON          EQU  0x48000000     ;Bus width & wait status
BANKCON0        EQU  0x48000004     ;Boot ROM control
BANKCON1        EQU  0x48000008     ;BANK1 control
BANKCON2        EQU  0x4800000c     ;BANK2 control
BANKCON3        EQU  0x48000010     ;BANK3 control
BANKCON4        EQU  0x48000014     ;BANK4 control
BANKCON5        EQU  0x48000018     ;BANK5 control
BANKCON6        EQU  0x4800001c     ;BANK6 control
BANKCON7        EQU  0x48000020     ;BANK7 control
REFRESH         EQU  0x48000024     ;DRAM/SDRAM refresh
BANKSIZE        EQU  0x48000028     ;Flexible Bank Size
MRSRB6          EQU  0x4800002c     ;Mode register set for SDRAM Bank6
MRSRB7          EQU  0x48000030     ;Mode register set for SDRAM Bank7


;==========================
; CLOCK & POWER MANAGEMENT
;==========================
LOCKTIME        EQU  0x4c000000     ;PLL lock time counter
MPLLCON         EQU  0x4c000004     ;MPLL Control
UPLLCON         EQU  0x4c000008     ;UPLL Control
CLKCON          EQU  0x4c00000c     ;Clock generator control
CLKSLOW         EQU  0x4c000010     ;Slow clock control
CLKDIVN         EQU  0x4c000014     ;Clock divider control


;=================
; INTERRUPT
;=================
SRCPND           EQU  0x4a000000    ;Interrupt request status
INTMOD           EQU  0x4a000004    ;Interrupt mode control
INTMSK           EQU  0x4a000008    ;Interrupt mask control
PRIORITY         EQU  0x4a00000c    ;IRQ priority control           <-- May

06, 2002 SOP
INTPND           EQU  0x4a000010    ;Interrupt request status
INTOFFSET        EQU  0x4a000014    ;Interruot request source offset
SUSSRCPND        EQU  0x4a000018    ;Sub source pending
INTSUBMSK        EQU  0x4a00001c    ;Interrupt sub mask


;=================
; I/O PORT for LED
;=================
GPFCON          EQU  0x56000050     ;Port F control
GPFDAT          EQU  0x56000054     ;Port F data
GPFUP           EQU  0x56000058     ;Pull-up control F

;Miscellaneous register
MISCCR          EQU  0x56000080     ;Miscellaneous control
DCKCON          EQU  0x56000084     ;DCLK0/1 control
EXTINT0         EQU  0x56000088     ;External interrupt control register 0
EXTINT1         EQU  0x5600008c     ;External interrupt control register 1
EXTINT2         EQU  0x56000090     ;External interrupt control register 2
EINTFLT0        EQU  0x56000094     ;Reserved
EINTFLT1        EQU  0x56000098     ;Reserved
EINTFLT2        EQU  0x5600009c     ;External interrupt filter control

register 2
EINTFLT3        EQU  0x560000a0     ;External interrupt filter control

register 3
EINTMASK        EQU  0x560000a4     ;External interrupt mask
EINTPEND        EQU  0x560000a8     ;External interrupt pending
GSTATUS0        EQU  0x560000ac     ;External pin status
GSTATUS1        EQU  0x560000b0     ;Chip ID(0x32440000)
GSTATUS2        EQU  0x560000b4     ;Reset type
GSTATUS3        EQU  0x560000b8     ;Saved data0(32-bit) before entering

POWER_OFF mode
GSTATUS4        EQU  0x560000bc     ;Saved data1(32-bit) before entering

POWER_OFF mode

;Added for 2440                                        ; DonGo
MSLCON                EQU  0x560000cc     ;Memory sleep control register

;=================
; WATCH DOG TIMER
;=================
WTCON         EQU  0x53000000       ;Watch-dog timer mode
WTDAT         EQU  0x53000004       ;Watch-dog timer data
WTCNT         EQU  0x53000008       ;Eatch-dog timer count


        END