Real-time debugging 101
----------------------------------------------------------
embedded rtos환경에서 생길 수 있는 문제 디버깅 방법
동기화문제 생기면 semaphore나 interrupt disable해라
stack overflow안나게 해라.
ISR구간에서 reg쓸때는 쓰기전에 저장했다 쓰고 복원해라.
http://www.embedded.com/columns/technicalinsights/186700660?_requestid=835183

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arm ez-5 보드에서 os만들어보기 블로그 식
http://kldp.org/blog/2942

예전에 (2004년)에 했던 ez-5상에서 윈도우os만들었던 기억이 새록새록 난다

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arm armulator

KB/embbeded sw 2008.03.17 20:38

http://www.arm.com/support/ARMulator.html



ARMulator benchmarking with RVD
http://www.arm.com/support/faqdev/1388.html
----------------------------------------
RVD supports cycle counting when connected to the RVISS via the RVD local host connection.  The information is displayed in the CycleCount tab of the RVD register pane.


(Note Cycle Counting is not available via the ARM-A-RR RDI connection to ARMulator in RVD).


RVD does not currently support ARMulator map files (as described in Application Note 93). This functionality will be added in a future release.



cached simulation
http://www.arm.com/support/faqdev/1339.html



Quick-start Guide for Benchmarking
http://www.arm.com/support/faqdev/4570.html

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ARM11 MPCore arm simulator


qemu 0.9.1 (opensource)
리눅스 상에서 동작 가능하다. 패치하고, 아쉽지만 아직 qemu for window는 0.9.0이다. 
http://fabrice.bellard.free.fr/qemu/download.html
리눅스 mpcore patch
http://www.arm.com/products/os/linux_download.html
아직 qemu에서 profiling하는 자료는 못찾겠네. 이게 없으면 시뮬레이션 해서 성능평가를 해볼수없으니 그냥 toy만들고 노는 거 되는거 아닌가.


RVDS 3.0
ARM에서 제공하는 것이니까 젤 나겠지만, 라이센스가 있어야겠지!
RVD(RealView Debugger)내부에 logic analyzer를 연결해서 그동안 실행한 instruction을 볼 수도 있고 profiler도 내장되어 있다.

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오후 12:50 2007-12-07
조경민 bro@shinbiro.com
verilog: blocking, nonblocking equal
===================================

assign 구문이나
assign Q2 =  ( (J&K&Clock) & ~Q2) |


always level sensitive ㅇ
always @( a or b ..)
 y = a | b;


일때만 = equal 쓰고



모든 always edge triggered인 경우는 <=를 쓴다.
<= 한 클럭 안에 모든 statement가 동시에 진행된다.
따라서 temporary 저장할 수 없다.
C = A+B;
D = C+1; 하면 A=1, B=1, C=0이면 C는 2, D는 2가 된다.


결국
D = C+1;
C = A+B;
를 한것과 동일하다. 코딩 순서에 의미가 있지 않다.



만일 A+B결과를 D에 반영하고 싶으면 현 클럭에서는 불가하다.
C = A+B;
D = A+B; 로 하든지


C = A+B;
t = A+B;한 후
다음 클럭에서
D = t 해야 한다.



C = A+B;
D = #2 C+1; 이렇게 delay를 줘도 결과는 동일하다. 다만 simulation시 지연이 보일 뿐이다.


 



(1)


always @(a or b or c)
begin
    temp = a + b;
    y = temp + c;
end


 


(2)
always @(posedge clk)
begin
    temp <= a + b;
    y <= temp + c;
end

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RTOS 추천책

KB/embbeded sw 2007.09.13 08:12


Real-Time System Design and Analysis : An Engineers Handbook (3/E)


Scheduling in Real-Time Systems


Software Engineering for Real-Time Systems


REALTIME SYSTEMS
http://kangcom.com/common/bookinfo/bookinfo.asp?sku=200009230001

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usb msc

KB/embbeded sw 2007.08.03 14:46
usb msc
http://www.lvr.com/mass_storage.htm


filesystem on a chip
http://www.ghielectronics.com/products.php

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Overview of Parallel IO
http://www.sesp.cse.clrc.ac.uk/Publications/paraio/paraio/node1.html

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SMP NUMA Paper

KB/embbeded sw 2007.08.01 14:15

95전 쯤 된 대학교 SMP or NUMA 관련 paper들
http://www.eecg.toronto.edu/parallel/pubs_abs.html#Unrau_etal_JSC94


http://www.eecg.toronto.edu/parallel/publications.html#ca


 

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open core!

KB/embbeded sw 2007.07.19 22:36

왠간한 core IP의 verilog 오픈 소스 버전을 볼 수 있다!
http://www.opencores.org


좋은 vhdl, verlog 정보 및 소스!
http://www.pldworld.ws



nnARM - ARM7TDMI clone (verilog)
http://www.pldworld.ws/_hdl/2/_ip/nnarm.htm

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서울대 병렬 처리
http://peace.snu.ac.kr/courses/parallelprocessing/

SMP, Cache Coherency, Memory Consistency...

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Shared Memory Consistency Models: A Tutorial Sarita V. Adve Kourosh Gharachorloo d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA
ftp://gatekeeper.dec.com/pub/DEC/WRL/research-reports/WRL-TR-95.7.pdf

Memory Consistency Models
http://www.cs.nmsu.edu/~pfeiffer/classes/573/notes/consistency.html

Multiprocessors Should Support Simple Memory-Consistency Models
http://www.cs.auckland.ac.nz/compsci703s1c/resources/MHill_sccase.pdf

Memory Consistency Models
http://www.cs.cornell.edu/courses/cs717/2001fa/lectures/sarita.ppt

http://en.wikipedia.org/wiki/Sequential_consistency

http://www.pldworld.ws/_hdl/1/erc.msstate.edu/www/%7Ereese/EE8063/html/multicpu_3/sld016.htm

A Unified Theory of Shared Memory Consistency
http://arxiv.org/abs/cs.DC/0208027

DSM memory consistency
http://blue.wonkwang.ac.kr/lecture/200201Lecture/dc/chapter7.ppt
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CE Requirements CE Requirements from a Supplier from a Supplier Perspective
http://www.axe-inc.co.jp/pr/pdf/ce-ogrt-axe1.pdf
The Open Group Real-time & Embedded Systems Forum
2005/01/23 Shozo TAKEOKA AXE,Inc

QoS API for multimedia
- PVR (recording/playing runs at same time)
- Network protocol stack comsume large CPU power on receiving many packet
   and MPEG-Player works less frame rate
- ex: MPEG and Network, Video and Audio
- CPU-power-ratio must be changed dynamically

Consumer Electronics (advanced automobile device)
- no hard realtime requirement
- Linux, NetBSD, WinCE, T-Engine
- CPU power resource management is required.
- response time not recommended hardly in ordinary application.

highend mobile (mobile phone) need realtime
- in special CPU for communication, iTron, VxWorks
mobile phone's application processor not need realtime
- WebBrowser, Email, movie MPEG4)
- well user interaction.
- fast startup

required API for Multicore, SMP.
- multicore is not SMP.
SMP has cache coherency
some multicore hasn't cache coherency
- processing an I/O device by Multicore has some problem.
Synchronization: not useful the technique for SMP, cache is incoherent.
   holding the processing data on cache.


QoS API for multicore, SMP
malloc_mclass( int size, storage class)
onchip SRAM
on board offchip SRAM
ordinary DRAM
uncachable DRAM

Uncachable area used for holding mutexes on Multicore CPU.
Uncachable area is good for non-cahce-coherency-system.
Uncachable area can be used for DMA
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MPSoC Scheduling

KB/embbeded sw 2006.09.16 10:49
Scheduling Anomaly Detection and Optimization for Distributed Systems with Preemptive Task-Sets
http://www.ida.ing.tu-bs.de/research/publications/ps/RE06:SchedAnomaDetecOptim.pdf

Scheduling Analysis Integration for Heterogeneous Multiprocessor SoC
http://citeseer.ist.psu.edu/cache/papers/cs2/517/http:zSzzSzwww.ida.ing.tu-bs.dezSzresearchzSzpublicationszSzpszSzRRE03:SchedAnalyIntegHeter.pdf/richter03scheduling.pdf

Scheduling of Multi-Task System Specifications
http://polimage.polito.it/~lavagno/esd/Madsen.pdf


A Hierarchical Multiprocessor Scheduling System for DSP Applications
어떻게 열지?
http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/asilomar/1995/7370/00/7370toc.xml&DOI=10.1109/ACSSC.1995.540525

Overview of real-time scheduling problems
http://www.ulb.ac.be/di/ssd/goossens/pms2004.pdf

Hierarchical Scheduling and Allocation of Multirate Systems on
Heterogeneous Multiprocessors
http://ieeexplore.ieee.org/iel3/4452/12625/00582347.pdf

NUMA
-------------------------------------------------

Multiprogrammed Parallel Application Scheduling in NUMA Multiprocessors
http://citeseer.ist.psu.edu/cache/papers/cs2/517/http:zSzzSzwww.ida.ing.tu-bs.dezSzresearchzSzpublicationszSzpszSzRRE03:SchedAnalyIntegHeter.pdf/richter03scheduling.pdf

Load Balancing Performance of Dynamic Scheduling on NUMA ...
http://www-2.cs.cmu.edu/~durand/papers/ieeeTPDS96.ps

Processor Pool-Based Scheduling for Large-Scale NUMA Multiprocessors
http://bcr2.uwaterloo.ca/~brecht/papers/getpaper.php?file=Zhou_Brecht_SM91.ps

Performance evaluation of Two-level Scheduling algorithms for NUMA multiprocessors
http://www3.interscience.wiley.com/cgi-bin/abstract/79561/ABSTRACT?CRETRY=1&SRETRY=0

A Flexible Thread Scheduler for Hierarchical Multiprocessor Machines
https://www.labri.fr/publications/paradis/2005/Thi05a/

A new scheduling strategy for NUMA multiprocessor systems
http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/proceedings/&toc=comp/proceedings/icpads/1996/7267/00/7267toc.xml&DOI=10.1109/ICPADS.1996.517567
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