Verilog, PLI, VPI

Verilog or System Verilog
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Verilog Tutorial
http://www.asic-world.com/verilog/index.html

System verilog and PLI Workshop
http://www.sutherland-hdl.com/papers.html

IEEE Verilog
http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945

VPI
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Ruby_VPI
http://ruby-vpi.rubyforge.org/doc/readme.html

ANVIL is a C++ interface to VPI.
http://anvil.sourceforge.net/

Teal is a C++ interface to VPI.
http://teal.sourceforge.net/

JOVE is a Java interface to VPI.
http://jove.sourceforge.net/

ScriptEDA is a Perl, Python, and Tcl interface to VPI.
http://embedded.eecs.berkeley.edu/Alumni/pinhong/scriptEDA/

RHDL is a hardware description and verification language based on Ruby.
http://rhdl.rubyforge.org/

MyHDL is a hardware description and verification language based on Python, which features conversion to Verilog and co-simulation.
http://myhdl.jandecaluwe.com/